Autor(s):

Petar Minev, Technical University of Gabrovo, Bulgaria, pminev@tugab.bg

https://doi.org/10.55630/STEM.2024.0612

Abstract:

    Visual simulation in circuit design involves creating a software application that provides a dynamic visual representation of a digital system modeled with Hardware Description Languages (HDLs). This allows users to gain a deeper understanding of the system’s behavior by observing the simulation in real-time. Additionally, the simulation data facilitates easier identification and correction of malfunctions in digital circuits models.
    This report explores the capabilities of the Visual Debug (VIZ) feature in the Makerchip IDE for creating a visual simulation of a stack-based calculator model. This model is specifically designed for online learning in digital hardware design courses offered by the Computer Systems and Technologies department at the Technical University of Gabrovo.

Keywords:

Visual Simulation; Digital Hardware Model; Stack-based Calculator; Makerchip IDE; Visual Debug;

Received:

30-09-2024

Accepted:

03-11-2024

Published:

20-12-2024

Cite (APA style):

Minev, P. (2024). Visual Simulation of a Digital Hardware Model, Science Series "Innovative STEM Education", volume 06, ISSN: 2683-1333, Institute of Mathematics and Informatics – Bulgarian Academy of Sciences, pp. 115-119, DOI: https://doi.org/10.55630/STEM.2024.0612

PDF file address:

http://www.math.bas.bg/vt/stemedu/books/06/STEM.2024.0612.pdf